1. Field of the Invention
The present invention relates generally to methods for forming patterned layers within microelectronic fabrications. More particularly, the present invention relates to methods for forming patterned chlorine containing plasma etchable silicon containing layers within microelectronic fabrications.
2. Description of the Related Art
Microelectronic fabrications are formed from microelectronic substrates over which are formed patterned microelectronic conductor layers which are separated by microelectronic dielectric layers.
As microelectronic fabrication integration levels have increased and patterned microelectronic conductor layer dimensions have decreased, it has become increasingly important within the art of microelectronic fabrication to form within microelectronic fabrications patterned microelectronic conductor layers, such as but not limited to: (1) gate electrodes within field effect transistors (FETs) within semiconductor integrated circuit microelectronic fabrications, as well as; (2) patterned microelectronic conductor interconnect layers, with uniform sidewall profile. Uniform sidewall profiles are particularly desirable within gate electrodes within field effect transistors (FETs) within semiconductor integrated circuit microelectronic fabrications since gate electrode linewidth and profile within a field effect transistor (FET) within a semiconductor integrated circuit microelectronic fabrication defines a channel width within the field effect transistor (FET) within the semiconductor integrated circuit microelectronic fabrication which in turn defines operational parameters of the semiconductor integrated circuit microelectronic fabrication within which is formed the field effect transistor (FET). Similarly, uniform sidewall profiles are desirable within patterned microelectronic conductor interconnect layers within microelectronic fabrications insofar as current carrying capacity of a patterned microelectronic conductor layer of diminished linewidth and enhanced aspect ratio is generally adversely affected by non-uniform sidewall profile.
While a uniform, and preferably perpendicular, sidewall profile is thus desirable within the art of microelectronic fabrication for forming patterned microelectronic conductor layers within microelectronic fabrications, uniform sidewall profiles are nonetheless not entirely readily achievable when forming, in general, patterned microelectronic conductor layers within microelectronic fabrications, and more particularly when forming gate electrodes within field effect transistors (FETs) within semiconductor integrated circuit microelectronic fabrications.
It is thus towards the goal of forming within a microelectronic fabrication a patterned microelectronic conductor layer, such as but not limited to a gate electrode within a field effect transistor (FET) within a semiconductor integrated circuit microelectronic fabrication, with enhanced sidewall profile uniformity, that the present invention is directed.
Various methods have been disclosed in the art of microelectronic fabrication for forming patterned microelectronic layers with desirable properties within microelectronic fabrications.
For example, Langley, in U.S. Pat. No. 5,271,799, discloses an anisotropic plasma etch method for forming with a uniform sidewall profile of at or near 90 degrees from a horizontal a patterned silicon oxide/metal silicide/polysilicon stack layer within a microelectronic fabrication. The anisotropic plasma etch method employs a single parallel plate plasma reactor chamber with a single inert cathode, where within the anisotropic plasma etch method there is varied within a silicon oxide etch step, a plasma power, an electrode spacing and a reactant gas composition in comparison with a metal silicide/polysilicon etch step within the anisotropic plasma etch method.
In addition, Cher et al., in U.S. Pat. No. 5,453,156, discloses an anisotropic plasma etch method for forming within an integrated circuit microelectronic fabrication a residue free patterned polysilicon layer or a residue free gate electrode structure, also with uniform sidewall profile. The method employs interposed between: (1) a main etch step employing a chlorine containing etchant gas composition when forming the residue free patterned polysilicon layer or the residue free gate electrode structure; and (2) an over etch step employing the chlorine containing etchant gas composition when forming the residue free patterned polysilicon layer or the residue free gate electrode structure, a passivation etch employing a fluorine containing etchant gas composition when forming the residue free patterned polysilicon layer or the residue free gate electrode structure within the integrated circuit microelectronic fabrication.
Further, Grewal, in U.S. Pat. No. 5,529,197, discloses an anisotropic plasma etch method for forming, with attenuated plasma charging damage, a polysilicon or a polycide stacked gate array within an integrated circuit microelectronic fabrication. The anisotropic plasma etch method employs a plasma reactor chamber having an upper inductive coil and a lower capacitive means, where the upper inductive coil is powered to a power of substantially less than 300 watts.
Finally, Fukuda et al., in U.S. Pat. No. 5,660,681, disclose an anisotropic plasma etch method for forming a residue free patterned silicon based material layer, such as a patterned polysilicon layer or a patterned polycide layer, within an integrated circuit microelectronic fabrication. The anisotropic plasma etch method employs: (1) a first plasma employing a first etchant gas composition comprising a non-fluorine halogen based chemical species and an oxygen based chemical species to form the patterned silicon based material layer having a non-stoichiometric silicon oxide sidewall protective layer formed thereupon, followed by; (2) a second plasma employing a second etchant gas composition comprising an oxygen based etchant gas composition for stripping from over the patterned silicon based material layer a patterned photoresist layer employed in defining the patterned silicon based material layer while simultaneously oxidizing the non-stoichiometric silicon oxide sidewall protective layer to form a stoichiometric silicon oxide sidewall protective layer, followed by; (3) stripping the substantially stoichiometric silicon oxide sidewall protective layer with a dilute hydrofluoric acid solution.
Desirable in the art of microelectronic fabrication are additional methods for forming within a microelectronic fabrication a patterned microelectronic conductor layer, such as but not limited to a gate electrode within a field effect transistor (FET) within a semiconductor integrated circuit microelectronic fabrication, with enhanced sidewall profile uniformity.
It is towards that object that the present invention is directed.
A first object of the present invention is to provide a method for forming within a microelectronic fabrication a patterned silicon containing layer, such as but not limited to a gate electrode within a field effect transistor (FET) within a semiconductor integrated circuit microelectronic fabrication.
A second object of the present invention is to provide a method in accord with the first object of the present invention, where the patterned silicon containing layer is formed with enhanced sidewall profile uniformity.
A third object of the present invention is to provide a method in accord with the first object of the present invention and the second object of the present invention, which method is readily commercially implemented.
In accord with the objects of the present invention, there is provided by the present invention a method for forming a patterned silicon containing layer within a microelectronic fabrication. To practice the method of the present invention, there is first provided a substrate. There is then formed over the substrate a blanket silicon containing layer. There is then formed over the blanket silicon containing layer a patterned photoresist layer. There is then etched, while employing a first plasma etch method in conjunction with the patterned photoresist layer as a first etch mask layer, the blanket silicon containing layer to form a partially etched blanket silicon containing layer. The first plasma etch method employs a first etchant gas composition comprising an etchant gas which upon plasma activation forms an active fluorine containing etchant species. There is then etched, while employing a second plasma etch method in conjunction with the patterned photoresist layer as a second etch mask layer, the partially etched blanket silicon containing layer to form a fully patterned silicon containing layer. The second plasma etch method employs a second etchant gas composition which upon plasma activation forms an active halogen containing etchant species other than an active fluorine containing etchant species.
The present invention also contemplates an embodiment which employs a blanket hard mask layer formed interposed between the blanket silicon containing layer and the patterned photoresist layer. Such an embodiment provides additional process latitude in forming the fully patterned silicon containing layer.
There is provided by the present invention a method for forming within a microelectronic fabrication a patterned silicon containing layer, such as but not limited to a gate electrode within a field effect transistor (FET) within a semiconductor integrated circuit microelectronic fabrication, where the patterned silicon containing layer is formed with uniform sidewall profile. The method of the present invention realizes the foregoing object by etching a blanket silicon containing layer from which is formed the patterned silicon containing layer first within a first plasma etch method employing a first etchant gas composition which upon plasma activation forms an active fluorine containing etchant species to form from the blanket silicon containing layer a partially etched blanket silicon containing layer. The partially etched blanket silicon containing layer is then etched within a second plasma etch method employing a second etchant gas composition which upon plasma activation forms an active halogen containing etchant species other than an active fluorine containing etchant species to form from the partially etched blanket silicon containing layer a fully patterned silicon containing layer.
The method of the present invention is readily commercially implemented. The present invention employs methods and materials as are otherwise generally known in the art of microelectronic fabrication. Since it is a process ordering and process control which provides at least in part the present invention, rather than the existence of methods and materials which provides the present invention, the present invention is readily commercially implemented.